R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 207

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(Example 3-1)
• Register specifications
BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_0 = H'0094, BAR_1= H'00055555,
BAMR_1 = H'00000000, BBR_1 = H'11A9, BDR_1 = H'78787878, BDMR_1 = H'0F0F0F0F,
BRCR = H'00000000
<Channel 0>
Address:
Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition)
<Channel 1>
Address:
Data:
Bus cycle: I bus/data access/write/byte
On channel 0, the setting of I bus/instruction fetch is ignored.
On channel 1, a user break occurs when the CPU writes byte data H'7x in address H'00055555
on the I bus.
H'00314156, Address mask: H'00000000
H'00055555, Address mask: H'00000000
H'00000078, Data mask: H'0000000F
Rev. 2.00 Sep. 07, 2007 Page 179 of 1164
Section 7 User Break Controller (UBC)
REJ09B0321-0200