R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 588

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R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.16 Overflow Flags in Reset Synchronous PWM Mode
When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3
bit in TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the
TCR_3 setting.
In reset synchronous PWM mode, with cycle register TGRA_3's set value at H'FFFF, when
specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up
to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both
cleared. At this point, TSR's overflow flag TCFV bit is not set.
Figure 12.122 shows a TCFV bit operation example in reset synchronous PWM mode with a set
value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified
without synchronous setting for the counter clear source.
Rev. 2.00 Sep. 07, 2007 Page 560 of 1164
REJ09B0321-0200
(H'FFFF)
TGRA_3
TCFV_3
TCFV_4
H'0000
Figure 12.122 Reset Synchronous PWM Mode Overflow Flag
TCNT_3 = TCNT_4
Counter cleared by compare match 3A
Not set
Not set

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