R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 150

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R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 6 Interrupt Controller (INTC)
6.3.3
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to
IRQ0 individually: low level, falling edge, rising edge, or both edges. ICR1 is initialized by a
power-on reset or in deep standby mode.
[Legend]
n = 7 to 0
Rev. 2.00 Sep. 07, 2007 Page 122 of 1164
REJ09B0321-0200
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
R/W:
Bit:
Interrupt Control Register 1 (ICR1)
IRQ7
R/W
Bit Name
IRQ71S
IRQ70S
IRQ61S
IRQ60S
IRQ51S
IRQ50S
IRQ41S
IRQ40S
IRQ31S
IRQ30S
IRQ21S
IRQ20S
IRQ11S
IRQ10S
IRQ01S
IRQ00S
15
1S
0
IRQ7
R/W
14
0S
0
IRQ6
R/W
13
1S
0
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IRQ6
R/W
12
0S
0
IRQ5
R/W
11
1S
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQ5
R/W
10
0S
0
Description
IRQ Sense Select
These bits select whether interrupt signals
corresponding to pins IRQ7 to IRQ0 are detected by a
low level, falling edge, rising edge, or both edges.
00: Interrupt request is detected on low level of IRQn
01: Interrupt request is detected on falling edge of IRQn
10: Interrupt request is detected on rising edge of IRQn
11: Interrupt request is detected on both edges of IRQn
IRQ4
R/W
1S
9
0
input
input
input
input
IRQ4
R/W
0S
8
0
IRQ3
R/W
1S
7
0
IRQ3
R/W
0S
6
0
IRQ2
R/W
1S
5
0
IRQ2
R/W
0S
4
0
IRQ1
R/W
1S
3
0
IRQ1
R/W
0S
2
0
IRQ0
R/W
1S
1
0
IRQ0
R/W
0S
0
0

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