R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 478

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.28 Timer Interrupt Skipping Counter (TITCNT)
TITCNT is an 8-bit readable/writable counter. The MTU2 has one TITCNT. TITCNT retains the
value even after TCNT_3 or TCNT_4 stops counting.
Note: Clear the T3AEN and T4VEN bits in TITCR to 0, to clear the value of TITCNT.
Rev. 2.00 Sep. 07, 2007 Page 450 of 1164
REJ09B0321-0200
Bit
7
6 to 4
3
2 to 0
Bit Name
—
3ACNT[2:0]
—
4VCNT[2:0]
Initial value:
Initial
Value
0
000
0
000
R/W:
Bit:
—
R/W
R
R
R
R
R
7
0
R
6
0
3ACNT[2:0]
Description
Reserved
This bit is always read as 0.
TGIA_3 Interrupt Counter
While the T3AEN bit in TITCR is set to 1, the count in
these bits is incremented every time a TGIA_3 interrupt
occurs.
[Clearing conditions]
•
•
•
Reserved
This bit is always read as 0.
TCIV_4 Interrupt Counter
While the T4VEN bit in TITCR is set to 1, the count in
these bits is incremented every time a TCIV_4 interrupt
occurs.
[Clearing conditions]
•
•
•
R
5
0
When the 3ACNT2 to 3ACNT0 value in TITCNT
matches the 3ACOR2 to 3ACOR0 value in TITCR
When the T3AEN bit in TITCR is cleared to 0
When the 3ACOR2 to 3ACOR0 bits in TITCR are
cleared to 0
When the 4VCNT2 to 4VCNT0 value in TITCNT
matches the 4VCOR2 to 4VCOR2 value in TITCR
When the T4VEN bit in TITCR is cleared to 0
When the 4VCOR2 to 4VCOR2 bits in TITCR are
cleared to 0
R
4
0
—
R
3
0
R
2
0
4VCNT[2:0]
R
1
0
R
0
0