R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 297

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

• Multiple Write Timing Setting Examples
Figures 9.33 to 9.35 show the correspondence between the timing of multiple write operations
involving 4 data units and the set values of the SDRAMm timing register (SDmTR). Table
9.13 shows the SDRAMm timing register (SDmTR) set values for each figure.
CKIO
SDRAM command
Data bus
CKIO
SDRAM command
Data bus
ACT: Row and bank activation command
RD:
PRA: Precharge-all command
(ACT-PRA)
DRAS
Figure 9.31 Multiple Read Timing Example 2
Figure 9.32 Multiple Read Timing Example 3
ACT
ACT: Row and bank activation command
RD:
PRA: Precharge-all command
(ACT-RD)
(ACT-PRA)
Read command
DRCD
DRAS
ACT
(ACR-RD)
Read command
DRCD
DSL
DSL
RD
(RD-d)
DCL
RD
(RD-d)
RD
DCL
Multiple read
RD
Multiple read
RD
RD
d0
Rev. 2.00 Sep. 07, 2007 Page 269 of 1164
RD
d0
RD
Section 9 Bus State Controller (BSC)
d1
PRA
d1
(PRA-next)
DPCG
PRA
d2
(PRA-next)
DPCG
DSL
d2
DSL
d3
REJ09B0321-0200
DSL
d3