R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 133

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.6.2
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously
(overlap), the interrupt controller (INTC) determines their relative priorities and starts processing
according to the results.
The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest
and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is
always accepted. The user break interrupt and H-UDI interrupt priority level is 15. Priority levels
of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be set freely
using the interrupt priority registers 01, 02, and 05 to 16 (IPR01, IPR02, and IPR05 to IPR16) of
the INTC as shown in table 5.9. The priority levels that can be set are 0 to 15. Level 16 cannot be
set. See section 6.3.1, Interrupt Priority Registers 01, 02, 05 to 16 (IPR01, IPR02, IPR05 to
IPR16), for details of IPR01, IPR02, and IPR05 to IPR16.
Table 5.9
Type
NMI
User break
H-UDI
IRQ
PINT
On-chip peripheral module 0 to 15
Interrupt Priority Level
Interrupt Priority Order
16
15
0 to 15
Priority Level
15
Comment
Fixed priority level. Cannot be masked
Fixed priority level
Fixed priority level
Set with interrupt priority registers 01, 02, and 05
to 16 (IPR01, IPR02, and IPR05 to IPR16)
Set with interrupt priority registers 01, 02, and 05
to 16 (IPR01, IPR02, and IPR05 to IPR16)
Rev. 2.00 Sep. 07, 2007 Page 105 of 1164
Section 5 Exception Handling
REJ09B0321-0200