R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 152

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Interrupt Controller (INTC)
[Legend]
n = 7 to 0
Rev. 2.00 Sep. 07, 2007 Page 124 of 1164
REJ09B0321-0200
Initial value:
Bit
15 to 8
7
6
5
4
3
2
1
0
Note:
R/W:
*
Bit:
Only 0 can be written to clear the flag after 1 is read.
Bit Name

IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
15
—
R
0
14
—
R
0
13
—
R
0
Initial
Value
All 0
0
0
0
0
0
0
0
0
12
—
R
0
11
—
R
0
R/W
R
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
10
—
R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
IRQ Interrupt Request
These bits indicate the status of the IRQ7 to IRQ0
interrupt requests.
Level detection:
0: IRQn interrupt request has not occurred
[Clearing condition]
•
1: IRQn interrupt has occurred
[Setting condition]
•
Edge detection:
0: IRQn interrupt request is not detected
[Clearing conditions]
•
•
1: IRQn interrupt request is detected
[Setting condition]
•
—
R
9
0
IRQn input is high
IRQn input is low
Cleared by reading IRQnF while IRQnF = 1, then
writing 0 to IRQnF
Cleared by executing IRQn interrupt exception
handling
Edge corresponding to IRQn1S or IRQn0S of
ICR1 has occurred at IRQn pin
—
R
8
0
R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0