R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 330

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Direct Memory Access Controller (DMAC)
• Interrupt request
• Reload function (source address, destination address, byte count) settable
• Rotate function settable
• DMAC stop/restart/suspend function settable
Notes: Terminologies in this section are as follows:
Rev. 2.00 Sep. 07, 2007 Page 302 of 1164
REJ09B0321-0200
 Two types of interrupt requests (generated when the byte count reaches "0")
• Interrupt request signals for each channel
• Interrupt request signal common to all channels
1. Single data transfer: Transfer in one read cycle and one write cycle by the DMAC (in
2. Single operand transfer: Continuous data transfer by the DMAC on one channel
3. One DMA transfer: Transferring a number of data, from the start address to the end
4. Channel number: n = 0 to 7
5. Request source number: k = 1 to 36, m = 0 to 36
6. BIU: Bus Interface Unit (peripheral module). One of the following four kinds according to
the case of dual address transfer)
(amount of data to be transferred is set in a register)
address set in the byte count register
the source or destination of transfer.
BIU_E:
BIU_P:
BIU_SH: Peripheral bus (2) (see figure 1.1)
External space (normal space and SDRAM space)
Peripheral bus (1) (see figure 1.1), on-chip RAM space