R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 865

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit 3 - Transmit Error Counter Warning Interrupt Flag (IRR3): This bit becomes set if the
transmit error counter (TEC) reaches a value greater than 95. The interrupt is reset by writing a '1'
to this bit position, writing '0' has no effect.
Bit 2 - Remote Frame Request Interrupt Flag (IRR2): Flag indicating that a remote frame has
been received in a mailbox. This bit is set if at least one receive mailbox, with related MBIMR not
set, contains a remote frame transmission request. This bit is automatically cleared when all bits in
the Remote Frame Receive Pending Register (RFPR), are cleared. It is also cleared by writing a '1'
to all the correspondent bit position in MBIMR. Writing to this bit has no effect.
Bit 1 – Data Frame Received Interrupt Flag (IRR1): IRR1 indicates that there are pending Data
Frames received. If this bit is set at least one receive mailbox contains a pending message. This bit
is cleared when all bits in the Data Frame Receive Pending Register (RXPR) are cleared, i.e. there
is no pending message in any receiving mailbox. It is in effect a logical OR of the RXPR flags
from each configured receive mailbox with related MBIMR not set. It is also cleared by writing a
'1' to all the correspondent bit position in MBIMR. Writing to this bit has no effect.
Bit 3: IRR3
0
1
Bit 2: IRR2
0
1
Bit 1: IRR1
0
1
Description
[Clearing condition] Writing 1 (Initial value)
Error warning state caused by transmit error
[Setting condition] When TEC ≥ 96
Description
[Clearing condition] Clearing of all bits in RFPR (Initial value)
at least one remote request is pending
[Setting condition] When remote frame is received and the corresponding
MBIMR = 0
Description
[Clearing condition] Clearing of all bits in RXPR (Initial value)
Data frame received and stored in Mailbox
[Setting condition] When data is received and the corresponding MBIMR = 0
Section 19 Controller Area Network (RCAN-ET)
Rev. 2.00 Sep. 07, 2007 Page 837 of 1164
REJ09B0321-0200