R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 782

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 I
(2)
In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer
clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For
transmit mode operation timing, refer to figure 17.14. The transmission procedure and operations
in transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS[3:0] bits in ICCR1. (Initial setting)
2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set.
3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is
Rev. 2.00 Sep. 07, 2007 Page 754 of 1164
REJ09B0321-0200
processing
(Output)
ICDRT
ICDRS
TDRE
SCL
TRS
SDA
User
transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous
transmission is performed by writing data to ICDRT every time TDRE is set. When changing
from transmit mode to receive mode, clear TRS while TDRE is 1.
Transmit Operation
[2] Set TRS
2
[3] Write data
C Bus Interface 3 (IIC3)
to ICDRT
Data 1
Bit 0
Figure 17.14 Transmit Mode Operation Timing
1
[3] Write data
to ICDRT
Bit 1
2
Data 1
Bit 6
7
Data 2
Bit 7
8
Bit 0
Data 2
1
Bit 6
7
[3] Write data
Bit 7
to ICDRT
8
Data 3
[3] Write data
Data 3
Bit 0
to ICDRT
1