R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 566

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R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(2)
A compare match signal is generated in the final state in which TCNT and TGR match (the point
at which the count value matched by TCNT is updated). When a compare match signal is
generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
After a match between TCNT and TGR, the compare match signal is not generated until the
TCNT input clock is generated.
Figure 12.87 shows output compare output timing (normal mode and PWM mode) and figure
12.88 shows output compare output timing (complementary PWM mode and reset synchronous
PWM mode).
Rev. 2.00 Sep. 07, 2007 Page 538 of 1164
REJ09B0321-0200
External
clock
TCNT input
clock
TCNT
Output Compare Output Timing
Figure 12.86 Count Timing in External Clock Operation (Phase Counting Mode)
Figure 12.87 Output Compare Output Timing (Normal Mode/PWM Mode)
TCNT input
clock
TCNT
TGR
Compare
match signal
TIOC pin
Rising edge
N - 1
N
N
N
Falling edge
N + 1
N - 1

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