R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 286

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R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 9 Bus State Controller (BSC)
Rev. 2.00 Sep. 07, 2007 Page 258 of 1164
REJ09B0321-0200
CKIO
SDRAM command
Data bus
CKIO
SDRAM command
Data bus
Figure 9.17 Multiple Write Timing Example (Multiple Write of 4 Data Units,
Figure 9.18 Multiple Write Timing Example (Multiple Write of 4 Data Units,
Shortest Timing Settings) Non-Consecutive Write Commands Issued
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all command
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all command
DSL: Deselect command
Shortest Timing Settings) Access Spanning Rows
ACT
ACT
WR
WR
d0
d0
Row address A
DSL
WR
d1
Multiple write
WR
WR
d2
d1
Multiple write
DSL
PRA
WR
ACT
d2
Row address B
DSL
WR
d3
PRA
WR
d3
PRA

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