R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 315

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The bus monitor is a module that monitors bus errors on each bus. When an illegal address access
or a bus timeout is detected, a bus error interrupt is generated and an access canceling signal is
output for the bus timeout. (The bus timeout function is used for debugging.)
Figure 10.1 shows a block diagram of the bus monitor.
10.1
The bus monitor has the following registers.
All registers are initialized by a power-on reset or in deep standby mode.
Table 10.1 Register Configuration
Register Name
Bus monitor enable register
Bus monitor status register 1
Bus monitor status register 2
Bus error control register
Peripheral
bus
Register Descriptions
Bus monitor
Figure 10.1 Block Diagram of Bus Monitor
Section 10 Bus Monitor
Bus monitor status register 1
Bus monitor status register 2
Abbreviation
SYCBEEN
SYCBESTS1
SYCBESTS2
SYCBESW
Bus monitor enable register
Bus error control register
R/W
R/W
R/W
R/W
R/W
H'00
H'00
Initial Value
H'00
H'00
Rev. 2.00 Sep. 07, 2007 Page 287 of 1164
Bus error signal
Address
H'FF400000
H'FF400004
H'FF400008
H'FF40000C 8, 16, 32
Section 10 Bus Monitor
REJ09B0321-0200
CPU core
SH2A
Access
Size
8, 16, 32
8, 16, 32
8, 16, 32