R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 161

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.4
There are six types of interrupt sources: NMI, user break, H-UDI, IRQ, PINT, and on-chip
peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the
highest. When set to level 0, that interrupt is masked at all times.
6.4.1
The NMI interrupt has a priority level of 16 and is accepted at all times. NMI interrupt requests
are edge-detected, and the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0)
selects whether the rising edge or falling edge is detected.
Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets the
interrupt mask level bits (I3 to I0) in the status register (SR) to level 15.
6.4.2
A user break interrupt which occurs when a break condition set in the user break controller (UBC)
matches has a priority level of 15. The user break exception handling sets the I3 to I0 bits in SR to
level 15. For user break interrupts, see section 7, User Break Controller (UBC).
6.4.3
The user debugging interface (H-UDI) interrupt has a priority level of 15, and occurs at serial
input of an H-UDI interrupt instruction. H-UDI interrupt requests are edge-detected and retained
until they are accepted. The H-UDI exception handling sets the I3 to I0 bits in SR to level 15. For
H-UDI interrupts, see section 26, User Debugging Interface (H-UDI).
Interrupt Sources
NMI Interrupt
User Break Interrupt
H-UDI Interrupt
Rev. 2.00 Sep. 07, 2007 Page 133 of 1164
Section 6 Interrupt Controller (INTC)
REJ09B0321-0200