R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 154
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
- Current page: 154 of 1196
- Download datasheet (8Mb)
Section 6 Interrupt Controller (INTC)
6.3.7
PIRR is a 16-bit register that indicates interrupt requests from external input pins PINT7 to
PINT0. PIRR is initialized by a power-on reset or in deep standby mode.
[Legend]
n = 7 to 0
Rev. 2.00 Sep. 07, 2007 Page 126 of 1164
REJ09B0321-0200
Bit
15 to 8
7
6
5
4
3
2
1
0
Initial value:
R/W:
Bit:
PINT Interrupt Request Register (PIRR)
Bit Name
PINT7R
PINT6R
PINT5R
PINT4R
PINT3R
PINT2R
PINT1R
PINT0R
15
—
0
R
14
—
0
R
13
—
0
R
Initial
Value
All 0
0
0
0
0
0
0
0
0
12
—
0
R
11
—
0
R
R/W
R
R
R
R
R
R
R
R
R
10
—
0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
PINT Interrupt Request
These bits indicate the status of the PINT7 to PINT0
interrupt requests.
0: No interrupt request at PINTn pin
1: Interrupt request at PINTn pin
—
R
9
0
—
R
8
0
PINT
7R
R
7
0
PINT
6R
R
6
0
PINT
5R
R
5
0
PINT
4R
R
4
0
PINT
3R
R
3
0
PINT
2R
R
2
0
PINT
1R
R
1
0
PINT
0R
R
0
0
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