R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 824

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 18 Serial Sound Interface (SSI)
(1)
Rev. 2.00 Sep. 07, 2007 Page 796 of 1164
REJ09B0321-0200
Transmission Using DMA Controller
Note: * If the SSI encounters an error interrupt underflow/overflow,
Yes
No
go back to the start in the flowchart again.
Figure 18.20 Transmission Using DMA Controller
Wait for interrupt from DMAC or SSI.
provide transmission data as
set SSICR configuration bits.
Set up DMA controller to
More data to be send?
disable error interrupts,
enable error interrupts.
Wait for idle interrupt
Disable SSI module,
enable Idle interrupt.
Release from reset,
Enable SSI module,
SSI error interrupt?
from SSI module.
End of Tx data?
disable DMA,
enable DMA,
required.
DMAC:
End*
Start
Yes
No
No
Yes
Define TRMD, EN, SCKD, SWSD,
MUEN, DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL, CHNL
EN = 1,
DMEN = 1,
UIEN = 1, OIEN = 1
EN = 0,
DMEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1