R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 258

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
9.4.13
SDmADR specifies the data bus width and the channel size of SDRAM.
Rev. 2.00 Sep. 07, 2007 Page 230 of 1164
REJ09B0321-0200
Bit
31 to 10 
9, 8
7 to 3
2 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
SDRAMm Address Register (SDmADR) (m = 0, 1)
Bit Name
DDBW[1:0] Undefined R/W

DSZ[2:0]
31
—
15
—
R
R
0
0
30
—
14
—
R
R
0
0
29
13
—
—
Initial
Value
All 0
All 0
Undefined R/W
R
R
0
0
28
12
—
—
R
R
0
0
27
11
—
—
R
R
0
0
R/W
R
R
26
10
—
—
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SDRAM Data Bit Width Setting
These bits specify the width of the SDRAM bus.
00: 8 bits
01: 16 bits
10: 32 bits
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Channel Size Setting
These bits specify the size of channels 0 and 1. If a
size smaller than SDRAM area 0 or 1 is selected, ghost
memory will result. When accessing 32-bit data in
SDRAM with a 16-bit bus width, the 16 bits of the first
half of the address (A1 = 0) are accessed first, and
then the 16 bits of the second half of the address (A1 =
1) are accessed.
DDBW[1:0]
R/W
25
—
—
R
0
9
R/W
24
—
—
R
0
8
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
19
—
—
R
R
0
3
0
R/W
18
—
—
R
0
2
DSZ[2:0]
R/W
17
—
—
R
0
1
R/W
16
—
—
R
0
0