R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 264

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R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 9 Bus State Controller (BSC)
9.4.17
SDCKSCNT enables or disables the clock stop control signal (internal signal in the chip) and
specifies the number of assert cycles.
Rev. 2.00 Sep. 07, 2007 Page 236 of 1164
REJ09B0321-0200
Bit
31 to 17 
16
15 to 8
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
SDRAM Clock Stop Control Signal Setting Register (SDCKSCNT)
Bit Name
DCKSEN
31
15
R
R
0
0
30
14
R
0
R
0
29
Initial
Value
All 0
0
All 0
13
R
0
R
0
28
12
R
0
R
0
27
11
R
0
R
0
R/W
R
R
R/W
26
10
R
0
R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Stop Control Signal Enable
This bit is used to enable or disable the clock stop
control signal. When enabled, the clock stop control
signal operates during transition to and from deep-
power-down mode and stops the CKIO (high level).
When disabled, the clock stop control signal stays low
level.
0: Clock stop control signal disabled
1: Clock stop control signal enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
25
R
0
R
9
0
24
R
0
R
8
0
R/W
23
R
0
7
0
R/W
22
R
0
6
0
R/W
21
R
0
5
0
DCKSC[7:0]
R/W
20
R
0
4
0
R/W
19
R
0
3
1
R/W
18
R
0
2
1
R/W
17
R
0
1
1
R/W
DCK
SEN
R/W
16
0
0
1

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