R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 272

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
(b) Page Access Operation
The initial data read/write operation is the same as a normal read/write operation. That is, when
the WAIT signal is low two cycles before the end of the wait cycles (Tend), external wait cycles
are inserted. After the WAIT signal has gone high, the wait cycles end (Tend) two cycles later.
In the second and subsequent read accesses, the page wait cycle is extended if the WAIT signal is
low two cycles before the end of the page access wait cycle (Tend), and the page wait cycles end
two cycles after the WAIT signal has gone high.
Figure 9.6 shows an example of external wait timing for page read access using longword (32-bit)
access to a 16-bit channel.
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CKIO
A27 to A0
WAIT
CSn
RD
WR
D31 to D0
Figure 9.6 External Wait Timing Example (Page Read Access to 16-Bit Channel)
Don't care
Ts
Cycle wait
A0
(Tend)
External
Don't care
wait
→
Tend
Page cycle
wait
A1
(Tend)
External
wait
→
Tend
Don't care