R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 381

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Cycle-stealing transfer mode
Pipelined transfer mode
[Legend]
DMA (S): Internal access cycle on DMAC source side
DMA (D): Internal access cycle on DMAC destination side
CKIO
DMA (S)
DMA (D)
DACK
DTEND (00)
DTEND (01)
DTEND (10)
DTEND (11)
DMINT_N
CKIO
DMA (S)
DMA (D)
DACK
DTEND (00)
DTEND (01)
DTEND (10)
DTEND (11)
DMINT_N
DTCM setting
DTCM setting
High
High
Single operand transfer (read 0 wait)
RD1
Single operand transfer (read 1 wait)
RD1 RD2 RD3 RD4
Figure 11.5 Timing of DMA End Signal Output
WR1
WR1 WR2 WR3 WR4
RD2
WR2
One DMA transfer
One DMA transfer
Single operand transfer (read 0 wait)
Section 11 Direct Memory Access Controller (DMAC)
RD1 RD2 RD3 RD4
RD1
Single operand transfer (read 1 wait)
WR1 WR2 WR3 WR4
Rev. 2.00 Sep. 07, 2007 Page 353 of 1164
Last read
of one DMA
transfer
WR1
Last read
of one DMA
transfer
Last write
of one DMA
transfer
RD2
Last write
of one DMA
transfer
End of
one DMA
transfer
REJ09B0321-0200
WR2
End of
one DMA
transfer