R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 876

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 Controller Area Network (RCAN-ET)
19.5.5
The RXPR0 is a 16-bit read/conditionally-write registers. The RXPR is a register that contains the
received Data Frames pending flags associated with the configured Receive Mailboxes. When a
CAN Data Frame is successfully stored in a receive mailbox the corresponding bit is set in the
RXPR. The bit may be cleared by writing a '1' to the corresponding bit position. Writing a '0' has
no effect. However, the bit may only be set if the mailbox is configured by its MBC (Mailbox
Configuration) to receive Data Frames. When a RXPR bit is set, it also sets IRR1 (Data Frame
Received Interrupt Flag) if its MBIMR (Mailbox Interrupt Mask Register) is not set, and the
interrupt signal is generated if IMR1 is not set. Please note that these bits are only set by receiving
Data Frames and not by receiving Remote frames.
• RXPR0
Note: * Only when writing a '1' to clear.
Bit 15 to 0 — Configurable receive mailbox locations corresponding to each mailbox position
from 15 to 0 respectively.
Rev. 2.00 Sep. 07, 2007 Page 848 of 1164
REJ09B0321-0200
Bit[15:0]: RXPR0
0
1
Initial value:
R/W:
Bit:
Data Frame Receive Pending Register 0 (RXPR0)
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
15
0
14
0
Description
[Clearing Condition] Writing '1' (Initial value)
Corresponding Mailbox received a CAN Data Frame
[Setting Condition] Completion of Data Frame receive on corresponding
mailbox
13
0
12
0
11
0
10
0
9
0
RXPR0[15:0]
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0