R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 157

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
6.3.10
DMA transfer request enable register 0 (DREQER0) is an 8-bit readable/writable register that
enables/disables the IIC3 DMA transfer requests, and enables/disables CPU interrupt requests.
DMA transfer request enable register 0 is initialized by a power-on reset or in deep standby mode.
Bit
3 to 0
Bit
7
6
5
4
3
2
1
0
*
Bit Name
Reserved
Reserved
IIC3 2ch TX
IIC3 2ch RX
IIC3 1ch TX
IIC3 1ch RX
IIC3 0ch TX
IIC3 0ch RX
DMA Transfer Request Enable Register 0 (DREQER0)
Bit Name
BN[3:0]*
Bits BN[3:0] are initialized at a manual reset.
Initial value:
Initial
Value
0000
Initial
Value
0
0
0
0
0
0
0
0
R/W:
Bit:
R/W
Reserved
0
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
0
6
Description
Bank Number
These bits indicate the bank number to which saving is
performed next. When an interrupt using register banks
is accepted, saving is performed to the register bank
indicated by these bits, and BN is incremented by 1.
After BN is decremented by 1 due to execution of a
RESBANK (restore from register bank) instruction,
restoration from the register bank is performed.
Description
DMA Transfer Request Enable Bits
These bits enable/disable DMA transfer requests, and
enable/disable CPU interrupt requests.
0: DMA transfer request disabled, CPU interrupt
1: DMA transfer request enabled, CPU interrupt request
2ch TX
R/W
IIC3
0
5
request enabled
disabled
2ch RX
R/W
IIC3
0
4
1ch TX
IIC3
R/W
0
3
1ch RX
Rev. 2.00 Sep. 07, 2007 Page 129 of 1164
IIC3
R/W
0
2
0ch TX
Section 6 Interrupt Controller (INTC)
R/W
IIC3
1
0
0ch RX
R/W
IIC3
0
0
REJ09B0321-0200