R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 280

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
(5)
An auto-refresh cycle starts when the auto-refresh operation enable bit (DRFEN) in SDRAM
refresh control register 1 (SDRFCNT1) is set to 1. After that refresh requests are issued at fixed
intervals, activating auto-refresh cycles. However, the activation of auto-refresh cycles may
sometimes be delayed because refresh requests are not accepted during read or write accesses.
A refresh request is issued immediately if the auto-refresh operation enable bit (DRFEN) in
SDRAM refresh control register 1 (SDRFCNT1) is set to 1 while auto-refresh is enabled.
The refresh counter is halted in self-refresh or deep-power-down mode. After recovery from self-
refresh or deep-power-down mode an auto-refresh cycle is activated, after which the counter value
is reset and the counter begins operating again
Make auto-refresh settings in SDRAM refresh control register 1 (SDRFCNT1). Note that refresh
cycles affect all SDRAM channels. Figure 9.9 shows an auto-refresh cycle timing example.
Rev. 2.00 Sep. 07, 2007 Page 252 of 1164
REJ09B0321-0200
Auto-Refresh
Figure 9.9 Auto-Refresh Cycle Timing Example (DREFW Bit Set Value: 0010)
CKIO
SDRAM command
DSL: Deselect command
RFA: Auto-refresh command
Auto-refresh cycle
RFA
DREFW
DSL
DSL