R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 388

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Direct Memory Access Controller (DMAC)
11.8.3
The settings of the DMA active signal output control bits for the source and destination (SACT or
DACT) in the corresponding DMA mode register control the output of the DMA active signal
(DACT) for a channel.
When SACT is set to 1, the DACT signal is activated in response to read access.
When DACT is set to 1, the DACT signal is activated in response to write access.
When both SACT and DACT are set to 1, the DACT signal is activated in response to read and
write access.
However, DACT signals are not activated for DMA requests from external peripheral circuits,
regardless of the setting of this bit.
The DMA acknowledge signal (DACK) is output throughout each single operand transfer.
Figure 11.11 is the timing chart for DMA acknowledge and DMA active signal output.
Note: The BSC is provided with a write buffer. Writing data to this buffer while writing to the
Rev. 2.00 Sep. 07, 2007 Page 360 of 1164
REJ09B0321-0200
DMA request
(ch 0)
DMA request
(ch 1)
DMA request
(ch 2)
DMA request
(ch 3)
DMA receive
channel
Notes: 1. Channels 0, 2 and 3 are set to level sensing.
external devices stops bus access in the chip. Because of this, in DMA transfer to or from
external devices, the DACT or DACK signal become disabled ("H") before the end of
external bus access. In this case, these signals are not synchronized with the external bus
access.
2. Channel 1 is set to edge sensing.
3. Thick lines indicate periods where the corresponding DREQ bits are set.
Output of the DMA Acknowledge and DNA Active Signals
ch2DMA
Figure 11.10 Overall Operation during Multiple DMA Requests
Masked period
(1)
ch3DMA
Masked period
(2)
ch0DMA
(3)
ch2DMA
(4)
ch3DMA
(5)
ch0DMA
(6)
ch1DMA
(7)
ch1DMA
(8)
ch3DMA
Masked period
(9)
ch3DMA