R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 868

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 Controller Area Network (RCAN-ET)
19.4.6
The Transmit Error Counter (TEC) and Receive Error Counter (REC) is a 16-bit read/(write)
register that functions as a counter indicating the number of transmit/receive message errors on the
CAN Interface. The count value is stipulated in the CAN protocol specification Refs. [2], [3], [4]
and [5]. When not in (Write Error Counter) test mode this register is read only, and can only be
modified by the CAN Interface. This register can be cleared by a Reset request (MCR0) or
entering to bus off.
In Write Error Counter test mode (i.e. TST[2:0] = B'100), it is possible to write to this register.
The same value can only be written to TEC/REC, and the value written into TEC is set to TEC
and REC. When writing to this register, RCAN-ET needs to be put into Halt Mode. This feature is
only intended for test purposes.
• TEC/REC (Address = H'00C)
Note: * It is only possible to write the value in test mode when TST[2:0] in MCR is B'100.
Rev. 2.00 Sep. 07, 2007 Page 840 of 1164
REJ09B0321-0200
Initial value:
R/W:
Bit:
Transmit Error Counter (TEC) and Receive Error Counter (REC)
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
REC is incremented during Bus Off to count the recurrences of 11 recessive bits as
requested by the Bus Off recovery sequence.
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0