R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 703

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
3
2
1, 0
Bit Name
STOP

CKS[1:0]
Initial
Value
0
0
00
R/W
R/W
R
R/W
Description
Stop Bit Length
Selects one or two bits as the stop bit length in
asynchronous mode. This setting is used only in
asynchronous mode. It is ignored in clocked
synchronous mode because no stop bits are added.
When receiving, only the first stop bit is checked,
regardless of the STOP bit setting. If the second stop
bit is 1, it is treated as a stop bit, but if the second stop
bit is 0, it is treated as the start bit of the next incoming
character.
0: One stop bit
1: Two stop bits
Reserved
This bit is always read as 0. The write value should
always be 0.
Clock Select
Select the internal clock source of the on-chip baud rate
generator. For further information on the clock source,
bit rate register settings, and baud rate, see section
16.3.8, Bit Rate Register (SCBRR).
00: Pφ
01: Pφ/4
10: Pφ/16
11: Pφ/64
Note: Pφ: Peripheral clock
Section 16 Serial Communication Interface with FIFO (SCIF)
When transmitting, a single 1-bit is added at the end
of each transmitted character.
When transmitting, two 1 bits are added at the end of
each transmitted character.
Rev. 2.00 Sep. 07, 2007 Page 675 of 1164
REJ09B0321-0200