R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 199

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
15
14
13
12
11 to 7
Bit Name
SCMFC0
SCMFC1
SCMFD0
SCMFD1

Initial
Value
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R
Description
C Bus Cycle Condition Match Flag 0
When the C bus cycle condition in the break conditions
set for channel 0 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 0 does not
1: The C bus cycle condition for channel 0 matches
C Bus Cycle Condition Match Flag 1
When the C bus cycle condition in the break conditions
set for channel 1 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 1 does not
1: The C bus cycle condition for channel 1 matches
I Bus Cycle Condition Match Flag 0
When the I bus cycle condition in the break conditions
set for channel 0 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 0 does not
1: The I bus cycle condition for channel 0 matches
I Bus Cycle Condition Match Flag 1
When the I bus cycle condition in the break conditions
set for channel 1 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 1 does not
1: The I bus cycle condition for channel 1 matches
Reserved
These bits are always read as 0. The write value
should always be 0.
match
match
match
match
Rev. 2.00 Sep. 07, 2007 Page 171 of 1164
Section 7 User Break Controller (UBC)
REJ09B0321-0200