R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 640

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 8-Bit Timers (TMR)
13.5.2
The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when the TCOR and TCNT
values match, the compare match signal is not generated until the next TCNT clock input. Figure
13.6 shows this timing.
13.5.3
When a compare match signal is generated, the timer output changes as specified by bits OS3 to
OS0 in TCSR. Figure 13.7 shows the timing when the timer output is toggled by the compare
match A signal.
Rev. 2.00 Sep. 07, 2007 Page 612 of 1164
REJ09B0321-0200
Pφ
Compare match A
signal
Timer output pin
Timing of CMFA and CMFB Setting at Compare Match
Timing of Timer Output at Compare Match
Pφ
TCNT
TCOR
Compare match
signal
CMF
Figure 13.7 Timing of Toggled Timer Output at Compare Match A
Figure 13.6 Timing of CMF Setting at Compare Match
N
N
N + 1