R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 204

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 User Break Controller (UBC)
7.4.4
When a user break interrupt request is received, the address of the instruction from where
execution is to be resumed is saved to the stack, and the exception handling state is entered. If the
C bus (FAB)/instruction fetch cycle is specified as a break condition, the instruction at which the
break should occur can be uniquely determined. If the C bus/data access cycle or I bus/data access
cycle is specified as a break condition, the instruction at which the break should occur cannot be
uniquely determined.
1. When C bus (FAB)/instruction fetch (before instruction execution) is specified as a break
2. When C bus (FAB)/instruction fetch (after instruction execution) is specified as a break
3. When C bus/data access cycle or I bus/data access cycle is specified as a break condition:
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condition:
The address of the instruction that matched the break condition is saved to the stack. The
instruction that matched the condition is not executed, and the break occurs before it.
However, when a delay slot instruction matches the condition, the instruction is executed, and
the branch destination address is saved to the stack.
condition:
The address of the instruction following the instruction that matched the break condition is
saved to the stack. The instruction that matches the condition is executed, and the break occurs
before the next instruction is executed. However, when a delayed branch instruction or delay
slot matches the condition, the instruction is executed, and the branch destination address is
saved to the stack.
The address after executing several instructions of the instruction that matched the break
condition is saved to the stack.
Value of Saved Program Counter