R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 32

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 1 Overview
Rev. 2.00 Sep. 07, 2007 Page 4 of 1164
REJ09B0321-0200
Item
Bus state controller
(BSC)
Bus monitor
Features
•
•
•
CSC
 Seven-channel chip select controller (CSC)
 External devices with their bus sizes of 32, 16, or 8 bits can be
 Cycle wait function
 The following features settable for wait controlling
 One-write strobe and byte write strobe modes are available as
 Page read and page write modes are available as page access
SDRAMC
 Two-channel external SDRAM interfaces
 Auto refresh using the internal programmable refresh counter or
 The following features settable
 Random column burst access available (one SDRAM burst length)
 Initialization sequencer issues precharge and auto refresh
Bus monitor function
When an illegal address access or a bus timeout is detected, a bus
error interrupt is generated.
connected
Up to 31 cycles (up to 7 cycles for page access cycle)
Timings of asserting and negating chip select signals
Timings of asserting and negating read/write signals
Timings of starting and stopping data output
write access modes
modes
self refresh mode selectable
Row-column latency, column latency, row-active period, write-
recovery period, row precharge period, auto refresh request
interval, initial precharge cycle count, and initial auto refresh
request interval
commands