R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 214

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 Cache
8.2
The cache has the following registers.
Table 8.2
8.2.1
The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all
instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF
bit controls disabling of all operand cache entries. The WT bit selects either write-through mode or
write-back mode for operand cache.
Programs that change the contents of CCR1 should be placed in an address space that is not
cached, and an address space that is cached should be accessed after reading the contents of
CCR1.
CCR1 is initialized to H'00000000 by a power-on reset and in deep standby but not initialized by a
manual reset or in software standby mode.
Rev. 2.00 Sep. 07, 2007 Page 186 of 1164
REJ09B0321-0200
Register Name
Cache control register 1
Cache control register 2
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Register Descriptions
Cache Control Register 1 (CCR1)


31
15
R
R
0
0
Register Configuration


30
14
R
R
0
0


29
13
R
R
0
0

28
12

R
R
Abbreviation
CCR1
CCR2
0
0
R/W
ICF

27
11
R
0
0

26
10

R
R
0
0

25

R
R
R/W
R/W
R/W
0
9
0
R/W
ICE
24

R
0
8
0
Initial Value
H'00000000
H'00000000
23


R
R
0
7
0
22


R
R
0
6
0
21


R
R
0
5
0
Address
H'FFFC1000 32
H'FFFC1004 32
20


R
R
0
4
0
OCF
R/W
19

R
0
3
0
18


R
R
0
2
0
Access Size
R/W
WT
17

R
0
1
0
OCE
R/W
16

R
0
0
0