R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 61

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Addressing Mode Instruction Format
PC relative
Immediate
disp:12
Rn
#imm:20
#imm:8
#imm:8
#imm:8
#imm:3
Effective Address Calculation
The effective address is the sum of PC value and
the value that is obtained by doubling the sign-
extended 12-bit displacement (disp).
The effective address is the sum of PC value and
Rn.
The 20-bit immediate data (imm) for the MOVI20
instruction is sign-extended.
The 20-bit immediate data (imm) for the MOVI20S
instruction is shifted by eight bits to the left, the
upper bits are sign-extended, and the lower bits
are padded with zero.
Sign-extended
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions is zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA
instruction is zero-extended and then quadrupled.
The 3-bit immediate data (imm) for the BAND,
BOR, BXOR, BST, BLD, BSET, and BCLR
instructions indicates the target bit location.
31
extended imm (20 bits)
(sign-extended)
Sign-
31 27
imm (20 bits) 00000000
PC
Rn
disp
PC
2
19
8
×
0
+
0
+
Rev. 2.00 Sep. 07, 2007 Page 33 of 1164
PC + disp × 2
PC + Rn
REJ09B0321-0200
Section 2 CPU
Equation
PC + disp × 2
PC + Rn
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