R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 206

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 User Break Controller (UBC)
(Example 1-3)
• Register specifications
(2)
(Example 2-1)
• Register specifications
(3)
Rev. 2.00 Sep. 07, 2007 Page 178 of 1164
REJ09B0321-0200
BAR_0 = H'00008404, BAMR_0 = H'00000FFF, BBR_0 = H'0054, BAR_1= H'00008010,
BAMR_1 = H'00000006, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000,
BRCR = H'00000020
<Channel 0>
Address:
Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not
<Channel 1>
Address:
Data:
Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not
A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed
or before an instruction with addresses H'00008010 to H'00008016 are executed.
BAR_0 = H'00123456, BAMR_0 = H'00000000, BBR_0 = H'0064, BAR_1= H'000ABCDE,
BAMR_1 = H'000000FF, BBR_1 = H'106A, BDR_1 = H'A512A512,
BDMR_1 = H'00000000, BRCR = H'00000000
<Channel 0>
Address:
Bus cycle: C bus/data access/read (operand size is not included in the condition)
<Channel 1>
Address:
Data:
Bus cycle: C bus/data access/write/word
On channel 0, a user break occurs with longword read from address H'00123456, word read
from address H'00123456, or byte read from address H'00123456. On channel 1, a user break
occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE.
Break Condition Specified for C Bus Data Access Cycle
Break Condition Specified for I Bus Data Access Cycle
H'00008404, Address mask: H'00000FFF
included in the condition)
H'00008010, Address mask: H'00000006
H'00000000, Data mask: H'00000000
included in the condition)
H'00123456, Address mask: H'00000000
H'000ABCDE, Address mask: H'000000FF
H'0000A512, Data mask: H'00000000