R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 682

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Realtime Clock (RTC)
Rev. 2.00 Sep. 07, 2007 Page 654 of 1164
REJ09B0321-0200
Bit
4
3
2, 1
0
Bit Name
CIE
AIE
—
AF
Initial
Value
0
0
All 0
0
R/W
R/W
R/W
R
R/W
Description
Carry Interrupt Enable Flag
When the carry flag (CF) is set to 1, the CIE bit enables
interrupts.
0: A carry interrupt is not generated when the CF flag is
1: A carry interrupt is generated when the CF flag is set
Alarm Interrupt Enable Flag
When the alarm flag (AF) is set to 1, the AIE bit allows
interrupts.
0: An alarm interrupt is not generated when the AF flag
1: An alarm interrupt is generated when the AF flag is
Reserved
These bits are always read as 0. The write value should
always be 0.
Alarm Flag
The AF flag is set when the alarm time, which is set by
an alarm register (ENB bit in RSECAR, RMINAR,
RHRAR, RWKAR, RDAYAR, RMONAR, or RYRAR is
set to 1), and counter match.
0: Alarm register and counter not match
[Clearing condition]
•
1: Alarm register and counter match *
[Setting condition]
•
Note:
set to 1
to 1
is set to 1
set to 1
When 0 is written to AF.
When alarm register (only a register with ENB bit
set to 1) and counter match
*
Writing 1 holds previous value.