R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 21

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

16.4 Operation ........................................................................................................................... 702
16.5 SCIF Interrupts .................................................................................................................. 721
16.6 Usage Notes ....................................................................................................................... 722
Section 17 I
17.1 Features.............................................................................................................................. 725
17.2 Input/Output Pins ............................................................................................................... 727
17.3 Register Descriptions ......................................................................................................... 728
17.4 Operation ........................................................................................................................... 744
17.5 Interrupt Requests .............................................................................................................. 762
16.3.10 FIFO Data Count Register (SCFDR) .................................................................... 698
16.3.11 Serial Port Register (SCSPTR) ............................................................................. 699
16.3.12 Line Status Register (SCLSR) .............................................................................. 701
16.4.1 Overview............................................................................................................... 702
16.4.2 Operation in Asynchronous Mode ........................................................................ 704
16.4.3 Operation in Clocked Synchronous Mode ............................................................ 713
16.6.1 SCFTDR Writing and TDFE Flag ........................................................................ 722
16.6.2 SCFRDR Reading and RDF Flag ......................................................................... 722
16.6.3 Restriction on DMAC Usage ................................................................................ 723
16.6.4 Break Detection and Processing ........................................................................... 723
16.6.5 Sending a Break Signal......................................................................................... 723
16.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 724
17.3.1 I
17.3.2 I
17.3.3 I
17.3.4 I
17.3.5 I
17.3.6 Slave Address Register (SAR).............................................................................. 741
17.3.7 I
17.3.8 I
17.3.9 I
17.3.10 NF2CYC Register (NF2CYC) .............................................................................. 743
17.4.1 I
17.4.2 Master Transmit Operation ................................................................................... 745
17.4.3 Master Receive Operation..................................................................................... 747
17.4.4 Slave Transmit Operation ..................................................................................... 749
17.4.5 Slave Receive Operation....................................................................................... 752
17.4.6 Clocked Synchronous Serial Format..................................................................... 753
17.4.7 Noise Filter ........................................................................................................... 757
17.4.8 Example of Use..................................................................................................... 758
2
2
2
2
2
2
2
2
2
2
C Bus Control Register 1 (ICCR1)..................................................................... 729
C Bus Control Register 2 (ICCR2)..................................................................... 732
C Bus Mode Register (ICMR)............................................................................ 734
C Bus Interrupt Enable Register (ICIER) ........................................................... 736
C Bus Status Register (ICSR)............................................................................. 738
C Bus Transmit Data Register (ICDRT)............................................................. 742
C Bus Receive Data Register (ICDRR).............................................................. 742
C Bus Shift Register (ICDRS)............................................................................ 742
C Bus Format...................................................................................................... 744
C Bus Interface 3 (IIC3) ................................................................725
Rev. 2.00 Sep. 07, 2007 Page xxi of xxviii