R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 140

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R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 5 Exception Handling
Rev. 2.00 Sep. 07, 2007 Page 112 of 1164
REJ09B0321-0200
Exception Type
Register bank error (underflow)
Trap instruction
Slot illegal instruction
General illegal instruction
Integer division instruction
Stack Status
SP
SP
SP
SP
SP
Jump destination address
of delayed branch instruction
SR
Address of instruction
after TRAPA instruction
Start address of general
illegal instruction
SR
SR
Start address of relevant
RESBANK instruction
Start address of relevant
integer division instruction
SR
SR
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits

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