R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 160

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Interrupt Controller (INTC)
6.3.13
DMA transfer request enable register 3 (DREQER3) is an 8-bit readable/writable register that
enables/disables the ADC, MTU2 (channels 0 to 4), and RCAN-ET (channels 0 and 1) DMA
transfer requests, and enables/disables CPU interrupt requests.
DMA transfer request enable register 3 is initialized by a power-on reset or in deep standby mode.
Rev. 2.00 Sep. 07, 2007 Page 132 of 1164
REJ09B0321-0200
Bit
7
6
5
4
3
2
1
0
Bit Name
ADC
MTU2 4ch
MTU2 3ch
MTU2 2ch
MTU2 1ch
MTU2 0ch
RCAN-ET 1ch 0
RCAN-ET 0ch 0
DMA Transfer Request Enable Register 3 (DREQER3)
Initial value:
Initial
Value
0
0
0
0
0
0
R/W:
Bit:
ADC
R/W
0
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MTU2
R/W
4ch
0
6
Description
DMA Transfer Request Enable Bits
These bits enable/disable DMA transfer requests, and
enable/disable CPU interrupt requests.
0: DMA transfer request disabled, CPU interrupt
1: DMA transfer request enabled, CPU interrupt request
MTU2
R/W
3ch
0
5
request enabled
disabled
MTU2
R/W
2ch
0
4
MTU2
R/W
1ch
0
3
MTU2
R/W
0ch
0
2
RCAN-ET
R/W
1ch
0
1
RCAN-ET
R/W
0ch
0
0