R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 77

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Instruction
CLIPS.B
CLIPS.W Rn
CLIPU.B
CLIPU.W Rn
DIV1
DIV0S
DIV0U
DIVS
DIVU
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT
EXTS.B
EXTS.W
EXTU.B
Rn
Rn
Rm,Rn
Rm,Rn
R0,Rn
R0,Rn
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Instruction Code
0100nnnn10010001
0100nnnn10010101
0100nnnn10000001
0100nnnn10000101
0011nnnnmmmm0100
0010nnnnmmmm0111
0000000000011001
0100nnnn10010100
0100nnnn10000100
0011nnnnmmmm1101
0011nnnnmmmm0101
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
Operation
When Rn > (H'0000007F),
(H'0000007F) → Rn, 1 → CS
when Rn < (H'FFFFFF80),
(H'FFFFFF80) → Rn, 1 → CS
When Rn > (H'00007FFF),
(H'00007FFF) → Rn, 1 → CS
When Rn < (H'FFFF8000),
(H'FFFF8000) → Rn, 1 → CS
When Rn > (H'000000FF),
(H'000000FF) → Rn, 1 → CS
When Rn > (H'0000FFFF),
(H'0000FFFF) → Rn, 1 → CS
1-step division (Rn ÷ Rm)
MSB of Rn → Q,
MSB of Rm → M, M ^ Q → T
0 → M/Q/T
Signed operation of Rn ÷ R0
→ Rn 32 ÷ 32 → 32 bits
Unsigned operation of Rn ÷ R0
→ Rn 32 ÷ 32 → 32 bits
Signed operation of Rn × Rm
→ MACH, MACL
32 × 32 → 64 bits
Unsigned operation of Rn ×
Rm → MACH, MACL
32 × 32 → 64 bits
Rn – 1 → Rn
When Rn is 0, 1 → T
When Rn is not 0, 0 → T
Byte in Rm is
sign-extended → Rn
Word in Rm is
sign-extended → Rn
Byte in Rm is
zero-extended → Rn
Rev. 2.00 Sep. 07, 2007 Page 49 of 1164
Execu-
tion
Cycles
1
1
1
1
1
1
1
36
34
2
2
1
1
1
1
T Bit




Calcu-
lation
result
Calcu-
lation
result
0




Com-
parison
result



SH2,
SH2E SH4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
REJ09B0321-0200
Section 2 CPU
Compatibility
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SH-2A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes