R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 706

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 07, 2007 Page 678 of 1164
REJ09B0321-0200
Bit
4
3
Bit Name
RE
REIE
Initial
Value
0
0
R/W
R/W
R/W
Description
Receive Enable
Enables or disables the SCIF serial receiver.
0: Receiver disabled*
1: Receiver enabled*
Notes: 1. Clearing RE to 0 does not affect the receive
Receive Error Interrupt Enable
Enables or disables the receive-error (ERI) interrupts
and break (BRI) interrupts. The setting of REIE bit is
valid only when RIE bit is set to 0.
0: Receive-error interrupt (ERI) and break interrupt
1: Receive-error interrupt (ERI) and break interrupt
Note: * ERI or BRI interrupt requests can be cleared by
(BRI) requests are disabled
(BRI) requests are enabled*
2. Serial reception starts when a start bit is
reading the ER, BR or ORER flag after it has
been set to 1, then clearing the flag to 0, or by
clearing RIE and REIE to 0. Even if RIE is set
to 0, when REIE is set to 1, ERI or BRI
interrupt requests are enabled. Set so If SCIF
wants to inform INTC of ERI or BRI interrupt
requests during DMA transfer.
flags (DR, ER, BRK, RDF, FER, PER, and
ORER). These flags retain their previous
values.
detected in asynchronous mode, or
synchronous clock input is detected in
clocked synchronous mode. Select the
receive format in SCSMR and SCFCR and
reset the receive FIFO before setting RE to 1.
2
1