R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 326

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Bus Monitor
10.2.3
The bus timeout detection function detects bus accesses whose cycles are extended to 768 cycles
or more.
(1)
Bus timeout errors occur in the following cases. This function should be used when debugging
software.
• A bus access is not completed on peripheral bus (1)
• The WAIT signal remains asserted during an external bus access
(2)
The operation when a bus timeout error occurs is explained below.
1. The timeout counter starts counting from the next cycle after the start of a bus access.
2. If the bus access is not completed in 768 cycles, a bus timeout occurs and an access canceling
3. The bus access is terminated.
4. The CPU processes the bus error.
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signal is asserted for 256 cycles.
Bus signals such as address, data, BC, read/write, and burst are held.
The timeout error is recorded in the bus monitor status register 1 (SYCBESTS1) or bus
monitor status register 2 (SYCBESTS2).
A bus error interrupt is generated and sent to the CPU.
Locked buses are all released.
Conditions of Bus Timeout Error Generation
Operation When a Bus Timeout Error is Generated
Bus Timeout Detection Function