R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 1187

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Instruction format ..................................... 34
Instruction set ........................................... 38
Integer division instructions ................... 109
Interrupt exception handling................... 106
Interrupt exception handling vectors
and priorities ........................................... 137
Interrupt priority level............................. 105
Interrupt response time ........................... 149
IRQ interrupts ......................................... 134
J
Jump table base register (TBR) ................ 22
L
List of registers ..................................... 1027
Load-store architecture ............................. 27
Local acceptance filter mask (LAFM).... 817
Logic operation instructions ..................... 51
LRU ........................................................ 185
M
Mailbox................................................... 808
Mailbox control ...................................... 809
Mailbox structure.................................... 812
Manual reset ........................................... 100
Master receive operation......................... 747
Master transmit operation ....................... 745
Measurement circuit ............................. 1141
Memory-mapped cache .......................... 196
Message control field.............................. 813
Message data fields................................. 818
Message receive sequence ...................... 861
Message transmission sequence.............. 859
Micro processor interface (MPI)............. 808
Module standby function ...................... 1011
MTU2 functions ..................................... 370
MTU2 interrupts ..................................... 533
MTU2 module timing ........................... 1129
MTU2 output pin initialization ............... 564
Multi mode.............................................. 883
Multi-function timer pulse unit 2
(MTU2)................................................... 369
Multiplexed pin table (Port A) ................ 921
Multiplexed pin table (Port B) ................ 923
Multiplexed pin table (Port C) ................ 925
Multiplexed pin table (Port D) ................ 927
Multiplexed pin table (Port E) ................ 928
Multiplexed pin table (Port F)................. 928
Multiply and accumulate register
high (MACH)............................................ 22
Multiply and accumulate register
low (MACL) ............................................. 22
Multiply/Multiply-and-
accumulate operations............................... 27
N
NaN........................................................... 66
NMI interrupt.......................................... 133
Noise filter .............................................. 757
Nonlinearity error.................................... 892
Non-numbers (NaN) ................................. 65
Note on making a transition to
deep standby mode................................ 1010
Note on using a PLL oscillation circuit..... 90
Note on using crystal resonator................. 89
O
Offset error.............................................. 892
On-chip peripheral module interrupts
On-chip RAM ......................................... 983
Operation in asynchronous mode............ 704
Operation in clocked synchronous mode 713
Rev. 2.00 Sep. 07, 2007 Page 1159 of 1164
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