R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 120

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Exception Handling
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
Rev. 2.00 Sep. 07, 2007 Page 92 of 1164
REJ09B0321-0200
Type
Interrupts
Instructions
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BRAF.
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N.
BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.
Exception Handling
On-chip peripheral modules
Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Slot illegal instructions (undefined code placed directly after a delayed
branch instruction *
instructions *
instruction)
3
, RESBANK instruction, DIVS instruction, and DIVU
1
, instructions that rewrite the PC *
A/D converter (ADC)
Multifunction timer pulse unit 2 (MTU2)
Realtime clock (RTC)
Watchdog timer (WDT)
I²C bus interface 3 (IIC3)
Direct memory access controller (DMAC)
Serial communication interface with FIFO
(SCIF)
Controller area network (RCAN-ET)
Serial sound interface (SSI)
8-bit timer (TMR)
2
, 32-bit
Priority
High
Low