R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 760

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 I
17.3.2
ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in the control part of the I
ICCR2 is initialized to H'7D by a power-on reset or deep standby mode.
Rev. 2.00 Sep. 07, 2007 Page 732 of 1164
REJ09B0321-0200
Bit
7
6
I
2
Bit Name
BBSY
SCP
2
C Bus Control Register 2 (ICCR2)
C Bus Interface 3 (IIC3)
Initial value:
Initial
Value
0
1
R/W:
Bit:
BBSY
R/W
7
0
R/W
R/W
R/W
R/W
SCP
6
1
Description
Bus Busy
Enables to confirm whether the I
released and to issue start/stop conditions in master
mode. With the clocked synchronous serial format, this
bit is always read as 0. With the I
is set to 1 when the SDA level changes from high to low
under the condition of SCL = high, assuming that the
start condition has been issued. This bit is cleared to 0
when the SDA level changes from low to high under the
condition of SCL = high, assuming that the stop
condition has been issued. Write 1 to BBSY and 0 to
SCP to issue a start condition. Follow this procedure
when also re-transmitting a start condition. Write 0 in
BBSY and 0 in SCP to issue a stop condition.
Start/Stop Issue Condition Disable
Controls the issue of start/stop conditions in master
mode. To issue a start condition, write 1 in BBSY and 0
in SCP. A retransmit start condition is issued in the
same way. To issue a stop condition, write 0 in BBSY
and 0 in SCP. This bit is always read as 1. Even if 1 is
written to this bit, the data will not be stored.
SDAO SDAOP SCLO
R/W
5
1
R/W
4
1
R
3
1
—
R
2
1
IICRST
R/W
1
0
2
C bus.
—
R
0
1
2
2
C bus is occupied or
C bus format, this bit