R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 278

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
Notes: 1. After writing 0 to EXENB, check to confirm that the EXENB bit has been cleared to 0.
Rev. 2.00 Sep. 07, 2007 Page 250 of 1164
REJ09B0321-0200
Function/Operation
Power-down
Deep-power-down
Address register settings
Timing register settings
Mode register settings
Clock stop control signal
settings
2. Do not fail to confirm that all status bits in the SDRAM status register (SDSTR) have
been cleared to 0 before rewriting this bit.
Register
SDPWDCNT
SDDPDCNT
SD0ADR,
SD1ADR
SD0TR,
SD1TR
SD0MOD,
SD1MOD*
SDCKSCNT
2
Conditions
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SDRAM access disabled (set in SDRAMCm*
Auto-refresh enabled (DRFEN = 1)
Self-refresh disabled (DSFEN/DSFENCI = 0)
Deep-power-down disabled (DDPD/DDPDCI = 0)
SDRAM access disabled (set in SDRAMCm*
Self-refresh disabled (DSFEN/DSFENCI = 0)
Auto-refresh disabled (DRFEN = 0)
Power-down disabled (DPWD/DPWDCI = 0)
Auto-refresh disabled (DRFEN = 0)
SDRAM access disabled (set in SDRAMCm*
Self-refresh disabled (DSFEN/DSFENCI = 0)
Power-down disabled (DPWD/DPWDCI = 0)
Deep-power-down disabled (DDPD/DDPDCI = 0)
Self-refresh in progress (DSFEN/DSFENCI = 1)
or
Self-refresh disabled (DSFEN/DSFENCI = 0)
Auto-refresh disabled (DRFEN = 0)
SDRAM access disabled (set in SDRAMCm*
SDRAM access disabled (set in SDRAMCm*
Self-refresh disabled (DSFEN/DSFENCI = 0)
Power-down disabled (DPWD/DPWDCI = 0)
Deep-power-down disabled (DDPD/DDPDCI = 0)
Deep-power-down disabled (DDPD/DDPDCI = 0)
1
1
1
1
1
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