R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 498

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)
Figure 12.20 shows an example of the setting procedure for cascaded operation.
(2)
Figure 12.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for
TCNT_1 and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
Rev. 2.00 Sep. 07, 2007 Page 470 of 1164
REJ09B0321-0200
Example of Cascaded Operation Setting Procedure
Cascaded Operation Example (a)
TCLKC
TCLKD
TCNT_2
TCNT_1
<Cascaded operation>
Cascaded operation
Set cascading
Figure 12.20 Cascaded Operation Setting Procedure
Start count
FFFD
Figure 12.21 Cascaded Operation Example (a)
0000
FFFE
FFFF
[1]
[2]
0000
[1] Set bits TPSC2 to TPSC0 in the channel 1
[2] Set the CST bit in TSTR for the upper and
0001
TCR to B'1111 to select TCNT_2 overflow/
underflow counting.
lower channel to 1 to start the count
operation.
0001
0002
0001
0000
FFFF
0000