R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 699

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

16.3.1
SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received,
LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is
automatically transferred to the receive FIFO data register (SCFRDR).
The CPU cannot read or write to SCRSR directly.
16.3.2
SCFRDR is a 16-byte FIFO register that stores serial receive data. The SCIF completes the
reception of one byte of serial data by moving the received data from the receive shift register
(SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored.
The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the
SCFRDR, the value is undefined.
When SCFRDR is full of receive data, subsequent serial data is lost.
SCFRDR is initialized to an undefined value by a power-on reset or in deep standby mode.
Receive Shift Register (SCRSR)
Receive FIFO Data Register (SCFRDR)
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
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R
7
7
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R
6
6
Section 16 Serial Communication Interface with FIFO (SCIF)
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R
5
5
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R
4
4
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R
3
3
Rev. 2.00 Sep. 07, 2007 Page 671 of 1164
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R
2
2
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R
1
1
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R
0
0
REJ09B0321-0200