R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 284

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
(9)
The following two types of read/write access are supported.
• Multiple read/multiple write
• Single read/single write
Multiple read/multiple write occurs in the following cases.
1. CPU burst access (cache replace)
2. Access with longword (32-bit) to the SDRAM data bus having 8-bit or 16-bit width
3. Access with word (16-bit) to the SDRAM data bus having 8-bit width
4. Multiple data transfer in DMA pipeline transfer
The access timing can be set independently for each channel using the SDRAMI timing register
(SDITR). Access timing examples are described below.
(a)
Figure 9.14 shows a timing example for multiple read of 4 units of data, and figure 9.15 for
multiple write of 4 units of data.
The number of DMA transfers performed will vary depending on factors such as the number of
transfers and the transfer data size per operand and the SDRAM bus width. Read commands or
write commands may or may not be issued consecutively in response to an access request from the
bus master. When read commands or write commands are not issued consecutively, a deselect
command is issued between them.
Furthermore, deactivation and activation are performed automatically when the SDRAM row
address changes during a DMA transfer operation.
Figure 9.16 shows a timing example for multiple read of 4 units of data, and figure 9.17 for
multiple write of 4 units of data, when read/write commands are not issued consecutively. Figure
9.18 shows a timing example for multiple write with a row address change.
The access timing is modified by means of settings in the SDRAMm timing register (SDmTR).
Rev. 2.00 Sep. 07, 2007 Page 256 of 1164
REJ09B0321-0200
Read/Write Access
Multiple Read/Multiple Write Access