R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 229

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. This enables the LSI to connect
directly with SRAM, SDRAM, and other memory storage devices, and external devices.
9.1
1. External address space
• A maximum of 64 Mbytes for the SDRAM and each for areas CS0 to CS6 (256 Mbytes for
• Ability to select the data bus width (8, 16, or 32 bits) independently for each address space
2. Normal space interface
• Supports an interface for direct connection to SRAM
• Cycle wait function: Maximum of 31 wait states (maximum of seven wait states for page
• Wait control
• Write access modes: One-write strobe and byte-write strobe modes
• Page access mode: Support for page read and page write (64-bit, 128-bit, and 256-bit page
3. SDRAM interface
• Ability to set SDRAM in up to two areas
• Refresh functions
• Ability to select the access timing (support for low column latency, column latency, and low
• Initialization sequencer function, power-down function, deep-power-down function, and mode
Figure 9.1 shows a block diagram of the BSC.
CS6)
access cycles)
 Ability to select the assert/negate timing for chip select signals
 Ability to select the assert/negate timing for the read strobe and write strobe signals
 Ability to select the data output start/end timing
 Ability to select the delay for chip select signals
units)
 Auto-refresh (on-chip programmable refresh counter)
 Self-refresh
active interval settings)
register setting function implemented on-chip
Features
Section 9 Bus State Controller (BSC)
Rev. 2.00 Sep. 07, 2007 Page 201 of 1164
Section 9 Bus State Controller (BSC)
REJ09B0321-0200