R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 363

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11.3.11 DMA Interrupt Control Register (DMICNT)
DMICNT controls DMA interrupts for the respective channels.
Note: Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel
Bit
31 to 24 DINTM
23 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
1. …24: channel 7).
Bit Name

R/W
31
15
—
R
0
0
R/W
30
14
—
R
0
0
R/W
29
13
—
R
0
0
Initial
Value
All 0
All 0
R/W
28
12
—
R
0
0
DINTM
R/W
27
11
—
R
0
0
R/W
R/W
R
R/W
26
10
—
R
0
0
Description
DMA Interrupt Control
These bits are used to control whether DMA transfer
end interrupts for the respective channels should be
generated for the interrupt controller.
When a bit is cleared to "0", interrupt requests for the
corresponding channel are not generated.
When these bits are set to "1", DMA transfer end
interrupts for the corresponding channel are generated
for the interrupt controller.
For details, see section 11.5.2, DMA Interrupt
Requests.
0: Interrupt disabled
1: Interrupt enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
25
—
R
0
9
0
R/W
24
—
R
0
8
0
Section 11 Direct Memory Access Controller (DMAC)
23
—
—
R
R
0
7
0
Rev. 2.00 Sep. 07, 2007 Page 335 of 1164
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
19
—
—
R
R
0
3
0
REJ09B0321-0200
18
—
—
R
R
0
2
0
17
—
—
R
R
0
1
0
16
—
—
R
R
0
0
0