R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 254

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
Note: Make settings that satisfy the specifications of the connected SDRAM before starting the
Rev. 2.00 Sep. 07, 2007 Page 226 of 1164
REJ09B0321-0200
Bit
7 to 4
3 to 0
initialization sequence.
Bit Name
DARFC
[3:0]
DARFI[3:0] Undefined R/W
Initial
Value
Undefined R/W
R/W
Description
Initialization Auto-Refresh Count
These bits specify the number of times auto-refresh is
to be performed in the SDRAM initialization sequence.
0000: Setting prohibited
0001: 1 time
1111: 15 times
Initialization Auto-Refresh Interval
These bits specify the interval at which auto-refresh
commands are issued in the SDRAM initialization
sequence.
0000: 3 cycles
0001: 4 cycles
0010: 5 cycles
1111: 18 cycles
:
: